Method and apparatus for reducing substrate bias voltage drop

ABSTRACT

A semiconductor device is provided with a conductive layer provided on a backside of a semiconductor substrate. The conductive layer helps maintain a uniform bias voltage over the substrate. The conductive layer can also be used to apply a bias voltage to the substrate and reduce the number of bias voltage distribution regions required.

BACKGROUND OF THE INVENTION

[0001] The invention relates to semiconductor devices and moreparticularly to a method and apparatus for reducing bias voltage dropswithin a substrate.

DESCRIPTION OF THE RELATED ART

[0002] Semiconductor devices which perform various functions areconstructed on semiconductor substrates using a variety of techniques.The integrated circuits are generally constructed on the upper, activesurface of a substrate or semiconductor wafer. It is common to provide asubstrate bias voltage Vbb via a plurality of well plugs, such as P-wellplugs. The Vbb bias voltage is typically provided by a voltage regulatoror a charge pump. The well plugs are electrically connected with thesubstrate through respective diffusion regions. The substrate biasvoltage Vbb is used to control the threshold voltage Vt of varioustransistors formed in the substrate and maintain a substantively uniformVt from transistor to transistor. If the substrate voltage Vbb differsacross the area of the substrate due to voltage drops it changes thethreshold voltage Vt characteristics of nearby transistors causing thetransistors to switch inappropriately.

[0003] It is known in the art to maintain a stable substrate biasvoltage Vbb over a large area of the substrate by spacing the well plugsclose together, however this occupies large substrate real estate. It isalso known to use a heavily doped substrates with a lightly dopedepitaxial layer to help stabilize the substrate voltage; however suchprocesses are expensive. It would be desirable to have a semiconductordevice and method of making the same that cost effectively reduces biasvoltage Vbb drop across the substrate, and which also reduces the numberof P-well plugs required to supply the bias voltage Vbb over a givensubstrate area.

SUMMARY OF THE INVENTION

[0004] The invention provides a conductive layer secured to a backsideof a semiconductor substrate to help maintain a more uniform level ofbias voltage within the substrate. The substrate has transistorsfabricated on its upper, active side and has P-well plugs on the upper,active side that electrically couple Vbb voltage from a Vbb voltagesource to the substrate. The conductive layer can be a conductivemetallic layer, a conductive paste, a conductive polymeric film, or aconductive metallic film and provides a path for removing unwantedvoltage or noise from the substrate to help maintain a uniform Vbbvoltage throughout the substrate. As a consequence, a more uniform biasvoltage Vbb is provided within the substrate and in particular in theproximity of the transistors and thus the number of P-well plugs used tosupply the Vbb voltage can be reduced. The backside conductive layer mayoptionally be directly connected to a Vbb bias source.

[0005] Different materials and methods are disclosed for forming and/orsecuring the conductive layer to the backside of the substrate. In oneexemplary embodiment the conductive layer is a metallic layer, which mayoptionally extend beyond the backside of the substrate to provide anarea for a wire bond connection to the Vbb bias source. In otherexemplary embodiments the conductive layer may be formed as a cureableconductive paste, a conductive polymeric film, or a thin conductivemetal film.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] These and other advantages and features of the invention will bemore readily understood from the following detailed description of theinvention which is provided in connection with the accompanyingdrawings.

[0007]FIG. 1 is a graphical representation of a change in transistorthreshold voltage Vt caused by variations in substrate bias voltage Vbb.

[0008]FIG. 2 is a side view of an integrated circuit semiconductordevice which is fabricated in accordance with the invention.

[0009]FIG. 3 is a block diagram of a semiconductor device voltage supplysystem with bias voltage Vbb connected to a P-well tie down and to aconductive layer used in the invention.

[0010]FIG. 4 is a top view of a semiconductor device with a conductivelayer attached to the backside of the substrate in accordance with theinvention.

[0011]FIG. 5 is a cross-sectional view of FIG. 4.

[0012]FIG. 6 is a schematic diagram of a typical processor system withwhich the invention may be used.

DESCRIPTION OF PREFERRED EMBODIMENTS

[0013] The invention will now be described with reference to a substrateof a semiconductor device which is biased by a Vbb voltage, which may beobtained from a pumped voltage source. It is understood that theinvention has broader applicability and may be used with a substrate ofany pumped or non-pumped semiconductor device, including processors andmemory devices with many different circuit and transistorconfigurations. Similarly, the process and resulting structure describedbelow are merely exemplary of the invention, as many modifications andsubstitutions can be made without departing from the spirit or scope ofthe invention.

[0014] The term “substrate” used in the following description mayinclude any semiconductor-based structure that has an exposed siliconsurface. Structure must be understood to include silicon, silicon-oninsulator (SOI), silicon-on sapphire (SOS), doped and undopedsemiconductors, epitaxial layers of silicon supported by a basesemiconductor foundation, and other semiconductor structures. Thesemiconductor need not be silicon-based. The semiconductor could besilicon-germanium, germanium, or gallium arsenide. When reference ismade to substrate in the following description, previous process stepsmay have been utilized to form regions or junctions in or on the basesemiconductor or foundation.

[0015] To help explain the invention a brief discussion of how thesubstrate bias voltage Vbb affects transistor operation is provided inconnection with FIG. 1. It is a graphical representation 9 of the changein the threshold voltage Vt of a typical NMOS transistor fabricated in asubstrate with variations in substrate bias voltage (Vbb). The x-axis isa measure of the bias voltage Vbb in volts and the y-axis measures thethreshold voltage Vt of a transistor in volts. For FIG. 1 the transistorwas designed to have a threshold voltage Vt of 0.65 Volts at a biasvoltage Vbb of −1 volts. FIG. 1 demonstrates that as the bias voltageVbb varies the transistor's threshold voltage Vt also varies.Accordingly, it is important to keep the Vbb bias voltage within asubstrate as uniform as possible to avoid localized changes oftransistor Vt which will affect transistor operation. However,variations in bias voltage Vbb occur due to unwanted voltage orelectrical noise that develops within and along a substrate. Some ofthis voltage comes from device “cross talk” while some of the unwantedvoltage or electrical noise is generated from the operation of thevarious transistors themselves. While FIG. 1 illustrates the impact ofsubstrate voltage drop on a transistor, it is understood that thepresent invention relates to semiconductor electrical elements ingeneral, such as transistors, resistors, capacitors, electrodes,amplifiers, inverters, and gates.

[0016] Referring now to FIG. 2, is a partial elevation view of asemiconductor device 100 fabricated in accordance with the presentinvention. The present invention provides a conductive layer 60, such asa metallic layer, conductive paste, conductive polymeric film, orconductive metallic film, on the back side 81 of a semiconductorsubstrate 10 to maintain a more uniform bias voltage Vbb throughoutsubstrate 10. The device 100 is shown with two exemplary MOSFETtransistors 40, 42 constructed on substrate 10 which is formed of asemiconductor material with a P-well region 13, in the upper portion ofsubstrate 10. Device 100 has top surface 91 and substrate upper surface79 and backside 81. Conductive layer 60 is shown attached to thebackside 81. Conductive layer 60 may be a metallic layer (firstembodiment), a conductive paste (second embodiment), a conductivepolymeric film (third embodiment), or a conductive metallic film (fourthembodiment). FIG. 2 shows conductive layer 60 formed as a metalliclayer. Wire bond 95 is shown connecting conductive layer 60 with bondingpad 85. Bonding pad 85 may be in electrical contact with bias voltageVbb source 92 and discussed with respect to FIGS. 3.

[0017] The FIG. 2 device 100 is merely exemplary of a typical solidstate semiconductor circuit which could be configured in numerous ways.Various transistors 40, 42, P-well plug diffusion regions 14, fieldoxide regions 12, source/drain regions 16, and resistors 18 may beformed on the upper surface 79 of the substrate 10 or in P-well 13. Thetransistors 40, 42 are shown formed on gate oxide region 46, with asilicide layer 45, gate electrode 43, and a dielectric cap layer 44. Thegate stacks 40, 42 are covered with a gate stack insulating layer orgate spacer 20 which may be silicon nitride. Gate insulation layer 20and substrate 10 are also covered with insulating layer 11 which istypically Borophosphosilicate glass (BPSG) or other suitable insulationmaterial. Openings are formed in insulating layer 11 and electricallyconductive plugs 30, 32, 34, and 36 are formed in the openings forcontact with diffusion regions 14, 16, 17 of the substrate 10. P-welltie down plugs 30 are conventionally used to apply the bias voltage Vbb92 to P-well 13 via P-well diffusion regions. Also shown are contactplugs 32 in contact with resistor 18 and contact plugs 34, 36 in contactwith source/drain regions 16.

[0018] P-well plugs 30 are made of a conductive material with lowresistance, such as tungsten or polysilicon, and serve as ohmic contactbetween the bias voltage Vbb source 92 shown in FIG. 3 and P-well 13.P-well plugs 30 may be connected to bias voltage Vbb 92 viametallization layer 90, bonding pads 83, and wire bonds 82 as shown inFIG. 4. The bias voltage Vbb 92 is transferred to P-well 13 from byP-well plugs 30 and P-well diffusion regions 14. Conductive layer 60 isshown wire bonded 95 to bonding pad 85.

[0019] In a first exemplary embodiment of the invention shown in FIG. 2the conductive layer 60 is, as noted, preferably formed as a metalliclayer. The metallic layer has a thickness preferably less than or equalto 10 mil. The conductive layer 60 may be secured to the backside 81 ofthe substrate 10 by a conductive adhesive, such as “Ablebond 8360”manufactured by ABLESTIK Labs, Inc. The conductive layer 60 ispreferably attached to the backside 81 after a fabricated wafer has beencut into individual semiconductor devices (dies) 100. The conductivelayer 60 may extend beyond the length of the substrate 10, as shown atthe left side of FIG. 2, to allow for attachment thereto of a bondingwire 95 which connects the conductive layer 60 to a bonding pad 85. Theoverall length of conductive layer 60 preferably extends no more thanapproximately 5 mils past substrate edge 8.

[0020] Conductive layer 60 should have a low resistivity preferably lessthan 1×10⁻⁸ Ohm-meter. Suitable metals, metal alloys, or compounds forconductive layer 60 may be selected from at least one of the followingmetals: copper (Cu), silver (Ag), alloy 42, gold (Au), iron (Fe), andaluminum (Al). Conductive layer 60 removes unwanted voltage orelectrical noise from substrate 10 thus reducing undesirable localizeddrops in the substrate bias voltage Vbb. Conductive layer 60 can bedirectly connected to bias voltage Vbb 92 (FIG. 3), for example, theunwanted noise signal can move vertically downward through substrate 10to conductive layer 60 and flow through wire bond 95 to bonding pad 85.From bonding pad 85 it can flow to Vbb source 92 (FIG. 3) by knowntechniques.

[0021] Although FIG. 2 shows conductive layer 60 electrically connectedto the bonding pad 85, benefits can also be achieved without directlyconnecting conductive layer 60 to bonding pad 85. In this case,conductive layer 60 attracts undesired voltages and or switching noisefrom localized regions of the substrate 10, such as P-well 13 andtransfers it to other regions of substrate 10 thereby minimizing localVbb voltage drops, such as at transistor gate stacks 40, 42.

[0022] In a second exemplary embodiment conductive layer 60 is formed ofa curable conductive paste such as “Ablebond 8360”. In this caseconductive paste 60 may have the same length as the substrate 10. Theconductive paste 60 may be a thermoplastic resin containing conductiveparticles. The conductive particles are preferably metal and may beselected from at least one of the following metals: copper (Cu), silver(Ag), gold (Au), iron (Fe), and nickel (Ni) particles. The conductivepaste 60 should have a resistivity less than 1×10⁻⁵ Ohm-meter,preferably less than 1×10⁻⁷ Ohm-meter. The conductive paste 60 shouldhave a thickness less than or equal to 1 mil, preferably less thanapproximately 0.5 mil. The cure time for the conductive paste 60 ispreferably less than 15 minutes. The conductive paste 60 may be cured byheat and/or ultraviolet light. Conductive paste 60 can be applied to thesubstrate backside 81 of the wafer after backgrind but prior to cuttingthe wafer into individual semiconductor devices 100. Conductive paste 60can be applied by spin coating, spraying, screen printing, or bladecoating the paste 60.

[0023] Like the conductive metallic layer described above, if conductivepaste 60 is not in direct electrical communication with bonding pad 85,it will still draw unwanted voltage or electrical noise away fromsubstrate 10 to help stabilize the operation of the electrical elementsof the device 100. Unwanted voltage noise in substrate 10 may exit thesubstrate 10 by moving vertically down substrate 10 to conductive paste60 where it is flows through the conductive paste 60. For example,transferred noise in conductive paste 60 may horizontally flow away fromgate stacks 40, 42 and re-enter substrate 10 in the proximity of P-welldiffusion regions 14. The noise can then flow from P-well diffusionregions 14 to P-well plugs 30. From the P-well plugs 30, the voltage canflow to bonding pads 83, via metalization layers 90, where it canfurther flow away from active areas of device 100.

[0024] In a third exemplary embodiment, conductive layer 60 is formed ofa conductive polymeric film, such as “FC-262(b)” made by HitachiCorporation. The conductive film 60 must be isotropically conductive,i.e., a three dimensional film, so that voltage is free to move in allthree dimensions. A two dimensional film would not allow unwanted noiseto move vertically through a two dimensional film. Conductive film 60may be a solid resin matrix containing conductive particles. Conductivefilm 60 preferably has a thickness greater than approximately 1 mil andpreferably less than approximately 3 mil. The conductive particles arepreferably selected from at least one of the following metals: copper(Cu), silver (Ag), gold (Au), iron (Fe), and nickel (Ni). Conductivefilm 60 should have a resistivity less than approximately 1×10⁻⁵Ohm-meter, preferably less than 1×10⁻⁷ Ohm-meter. A conductive film 60can be applied to the wafer backside 81 after backgrind but prior tocutting the wafer into individual semiconductor devices 100. Conductivefilm 60 can be applied by applying pressure greater than approximately 1MegaPascal (MPa) to the film and/or wafer, and preferably a pressurebetween approximately 1 to 5 (MPa) for preferably about 5 seconds orless. The conductive film 60 should be applied at a temperature greaterthan 175 degrees Celsius, and preferably a temperature range ofapproximately 175 to 400 degrees Celsius. Conductive film 60, like theconductive paste, will draw unwanted voltage or electrical noise awayfrom substrate 10 in the manner described above with respect to theconductive paste.

[0025] In a fourth exemplary embodiment, conductive layer 60 is formedof a conductive metallic film 60. The conductive film 60 preferablyshould have a thickness less than or equal to approximately 1 mil and ispreferably formed of conductive particles selected from the followingmetals: copper (Cu), silver (Ag), gold (Au), iron (Fe), and nickel (Ni).Conductive film 60 should have a resistivity less than approximately1×10⁻⁵ Ohm-meter, preferably less than 1×10⁻⁸ Ohm-Meter. Conductive film60 can be applied to the substrate backside 81 after backgrind but priorto the cutting of the wafer into individual semiconductor devices. Theconductive film 60 can be applied by any of the following methods ortechniques: electroless plating, electrolytic plating, molecular beamepitaxy (MBE), vapor phase epitaxy (VPE), physical vapor deposition(PVD), chemical vapor deposition (CVD) and metal organic chemical vapordeposition (MOCVD). Like the conductive paste, conductive metallic film60 draws unwanted voltage or electrical noise away from substrate 10 inthe same manner as described above with respect to the conductive paste.

[0026]FIG. 3 is a block diagram of a semiconductor device voltage supplysystem 200 which includes a substrate bias voltage Vbb source 92. Shownare an external voltage supply Vcc 97 which supplies voltage to Vbbsource 92 via electrical contact 120. Vbb source 92 is shown supplied toP-well 13 through electrical contact 122, lead finger 87, wire bond 82,bonding pad 83, metalization layer 90, P-well contact plug 30, andP-well diffusion region 14. Conductive layer 60 is shown electricallyconnected to Vbb 92 via wire bond 95, bonding pad 85 and electricalcontact 121.

[0027] Exemplary voltage values for bias voltage Vbb 92 are −1 volts and0 volts. If conductive layer 60 is a metallic layer it is relativelyeasy to electrically connect it to Vbb source 92 in the manner shown anddescribed with reference to FIGS. 2 and 3. If the conductive layer 60 isa conductive paste, conductive polymeric film, or conductive metallicfilm they may also be electrically connected to Vbb source 92 through awire or other connection. However as noted earlier, the impact of noiseis still reduced even if conductive layer 60 is not in direct electricalcommunication to Vbb source 92.

[0028]FIG. 4 is a top view of the FIG. 2 semiconductor device 100fabricated in accordance with the invention. Lead fingers 87 are shownsecured to the top side 91 of device 100. The device 100 has aconductive layer 60 secured to the back side of the device 100 andextending past the device perimeter 101. Bonding pads 83, 85 typicallyare provided over an exterior surface area of the completed device 100,such as top surface 91, and may be located on the perimeter or centeredon the top surface 91 as shown in FIG. 4.

[0029] After fabrication is complete the semiconductor device 100 may besecured to a lead frame (not shown) via lead fingers 87 as shown in FIG.4. Bonding pad 85 of device 100 is shown bonded to the conductive layer60 by a wire bond 95. Bonding pad 85 can be configured to be inelectrical communication with substrate bias voltage Vbb source 92. Thusone path for removing noise from substrate 10 is for the noise to travelthrough the substrate 10 to conductive layer 60 to bonding pad 85 viawire bond 95. The remaining bonding pads 83 which are not in contactwith conductive layer 60 are shown connected to lead fingers 87 by wirebonds 82 in accordance with the electrical requirements of the circuitdesign. The wire bonding can be performed with various methods andmaterials known in the art. Even if bonding 85 is not directly connectedto Vbb source 92, the negative impact of unwanted substrate voltage ornoise can still be reduced.

[0030]FIG. 5 is a cross-sectional view of FIG. 4 taken at line V-V.Conductive layer 60 is shown attached to the substrate bottom surface 81with a conductive adhesive 62. Lead fingers 87 are shown attached to thetop surface 91 of device 100 by a conductive adhesive compound 94 usingwell known lead on chip techniques. Also shown is bonding pad 85 whichis in electrical communication with conductive layer 60 via wire bond82.

[0031]FIG. 6 illustrates a typical processor based system 102, includinga DRAM memory device 108 and at least one or both of the processor andmemory devices are fabricated according to the invention as describedabove. A processor based system, such as a computer system 102,generally comprises a central processing unit (CPU) 112, for example amicroprocessor, that communicates with one or more input/output devices104, 106 over a bus 118. The computer system 102 also includes a readonly memory device (ROM) 110 and may include peripheral devices such asfloppy disk drive 114 and a CD ROM drive 116 which also communicateswith the CPU 112 over the bus 118. At least one of the CPU 112, ROM 110and DRAM 108 has a conductive layer 60 attached to the backside of itssubstrate as described above.

[0032] Having thus described in detail preferred embodiments of thepresent invention, it is to be understood that the invention defined bythe appended claims is not to be limited by particular details set forthin the above description as many apparent variations thereof arepossible without departing from the spirit or scope of the invention.Accordingly, the above description and accompanying drawings are onlyillustrative of preferred embodiments which can achieve the features andadvantages of the present invention. It is not intended that theinvention be limited to the embodiments shown and described in detailherein. The invention is only limited by the scope of the followingclaims.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. A semiconductor device comprising: asemiconductor substrate; at least one electrical element circuitfabricated on an upper side of said substrate; a plurality of biasvoltage distribution regions fabricated over said upper side of saidsubstrate for receiving a bias voltage and providing said bias voltageto said substrate; and a conductive layer provided on a back side ofsaid substrate.
 2. The semiconductor device of claim 1, wherein saidelectrical element comprises at least one electrical element selectedfrom the group consisting of transistors, resistors, capacitors,electrodes, amplifiers, inverters, and gates.
 3. The semiconductordevice of claim 1, wherein said conductive layer is electrically coupledto a terminal supplying said bias voltage.
 4. The semiconductor deviceof claim 1 further comprising a plurality of conductive plugs forrespectively coupling said bias voltage source to said distributionregions.
 5. The semiconductor device of claim 1, wherein said conductivelayer comprises a conductive metallic layer.
 6. The semiconductor deviceof claim 5, wherein said conductive metallic layer has a thickness ofless than or equal to 10 mil.
 7. The semiconductor device of claim 5,wherein said conductive metallic layer is secured to the backside ofsaid substrate with a conductive adhesive.
 8. The semiconductor deviceof claim 5, wherein said conductive metallic layer is electricallycoupled to a terminal supplying said bias voltage.
 9. The semiconductordevice of claim 5, wherein said conductive metallic layer has aresisitivity less than 1×10⁻⁸ Ohm-meter.
 10. The semiconductor device ofclaim 5, wherein said conductive metallic layer comprises at least onematerial selected from the group consisting of copper (Cu), silver (Ag),alloy 42, gold (Au), iron (Fe), and aluminum (Al).
 11. The semiconductordevice of claim 10, wherein said conductive metallic layer is formed ofat least one material selected from the group consisting of: copper(Cu), silver (Ag), alloy 42, gold (Au), iron (Fe), and aluminum (Al).12. The semiconductor device of claim 5, wherein said metallic layer hasat least one length which exceeds a length of said substrate.
 13. Thesemiconductor device of claim 1, wherein said conductive layer comprisesa cured conductive paste.
 14. The semiconductor device of claim 13,wherein said conductive paste has a thickness of less than or equal to 1mil.
 15. The semiconductor device of claim 13, wherein said conductivepaste has a resistivity less than 1×10⁻⁵ Ohm-meter.
 16. Thesemiconductor device of claim 13, wherein said conductive pastecomprises a material with conductive particles therein.
 17. Thesemiconductor device of claim 16, wherein said conductive particlescomprise at least one of the group consisting of: copper (Cu), silver(Ag), gold (Au), iron (Fe), and nickel (Ni).
 18. The semiconductordevice of claim 1, wherein said conductive layer comprises anisotropically conductive polymeric film.
 19. The semiconductor device ofclaim 18, wherein said conductive polymeric film has a thickness greaterthan 1 mil.
 20. The semiconductor device of claim 18, wherein saidconductive polymeric film has a resistivity less than 1×10⁻⁵ Ohm-meter.21. The semiconductor device of claim 18, wherein said conductivepolymeric film comprises at least one conductive particle selected fromthe group consisting of: copper (Cu), silver (Ag), gold (Au), iron (Fe),and nickel (Ni).
 22. The semiconductor device of claim 1, wherein saidconductive layer comprises a conductive metallic film.
 23. Thesemiconductor device of claim 22, wherein said conductive metallic filmhas a thickness of less than or equal to 1 mil.
 24. The semiconductordevice of claim 22, wherein said conductive metallic film has aresistivity less than 1×10⁻⁵ Ohm-meter.
 25. The semiconductor device ofclaim 22, wherein said conductive metallic film comprises at least onematerial selected from the group consisting of: copper (Cu), silver(Ag), gold (Au), iron (Fe), and nickel (Ni).
 26. The semiconductordevice of claim 25, wherein said conductive metallic film is formed ofat least one material selected from the group consisting of copper (Cu),silver (Ag), gold (Au), iron (Fe), and nickel (Ni).
 27. Thesemiconductor device of claim 1, wherein said device is a memory device.28. The semiconductor device of claim 27, wherein said memory device isa dynamic random access memory (DRAM) device.
 29. The semiconductordevice of claim 1, wherein said device is a logic device.
 30. Thesemiconductor device of claim 1, wherein said device is a processordevice.
 31. A method of forming a semiconductor device, said methodcomprising: fabricating at least one electrical element on an upper sideof a semiconductor substrate; fabricating a plurality of bias voltagedistribution regions over said upper side of said substrate forreceiving a bias voltage and applying said bias voltage to saidsubstrate; and securing a conductive layer to a backside of saidsubstrate.
 32. The method of claim 31, wherein said electrical elementcomprises at least one electrical element selected from the groupconsisting of transistors, resistors, capacitors, electrodes,amplifiers, inverters, and gates.
 33. The method of claim 31, whereinsaid conductive layer comprises a conductive metallic layer.
 34. Themethod of claim 33, said conductive metallic layer has a thickness ofless than or equal to 10 mil.
 35. The method of claim 33, wherein saidconductive metallic layer is secured to said substrate backside with aconductive adhesive.
 36. The method of claim 33, further comprisingcoupling said conductive metallic layer to a terminal for supplying saidbias voltage.
 37. The method of claim 33, wherein said conductivemetallic layer has a resisitivity less than between 1×10⁻⁸ Ohm-meter.38. The method of claim 33, wherein said conductive metallic layercomprises at least one material selected from the group consisting of:copper (Cu), silver (Ag), alloy 42, gold (Au), iron (Fe), and aluminum(Al).
 39. The method of claim 38, wherein said conductive metallic layeris formed of as least one material selected from the group consistingof: copper (Cu), silver (Ag), alloy 42, gold (Au), iron (Fe), andaluminum (Al).
 40. The method of claim 33, wherein said conductivemetallic layer has at least one length which exceeds a length of saidsubstrate.
 41. The method of claim 33, wherein said conductive metalliclayer is applied to said substrate back side after a fabricated wafer iscut into individual semiconductor devices.
 42. The method of claim 31,further comprises providing a plurality of conductive plugs forrespectively coupling a received bias voltage source to saiddistribution regions.
 43. The method of claim 31, wherein saidconductive layer comprises a cured conductive paste.
 44. The method ofclaim 43, wherein said conductive paste has a thickness less than orequal to 1 mil.
 45. The method of claim 43, wherein said conductivepaste has a resistivity less than 1×10⁻⁵ Ohm-meter.
 46. The method ofclaim 43, wherein said conductive paste is formed of a materialcomprising conductive particles.
 47. The method of claim 43, whereinsaid conductive paste comprises conductive particles selected from atleast one of the group consisting of: copper (Cu), silver (Ag), gold(Au), iron (Fe), and nickel (Ni).
 48. The method of claim 43, furthercomprising applying said conductive paste to the backside of afabricated wafer after the wafer is background and before the wafer iscut into individual semiconductor devices.
 49. The method of claim 31,wherein said conductive layer comprises an isotropically conductivepolymeric film.
 50. The method of claim 49, wherein said conductivepolymeric film has a thickness greater than about 1 mil.
 51. The methodof claim 49, wherein said conductive polymeric film has a resistivityless than 1×10⁻⁵ Ohm-meter.
 52. The method of claim 49, wherein saidconductive polymeric film comprises conductive particles selected fromat least one of the group consisting of: copper (Cu), silver (Ag), gold(Au), iron (Fe), and nickel (Ni).
 53. The method of claim 49, furthercomprising applying said conductive polymeric film to the backside of afabricated wafer after said wafer is background and before said wafer iscut into individual semiconductor devices.
 54. The method of claim 49,wherein said conductive polymeric film is applied at a temperaturegreater than about 175 degrees Celsius.
 55. The method of claim 49,wherein said conductive polymeric film is pressed against said substrateat a pressure greater than 1 mega Pascal.
 56. The method of claim 31,wherein said conductive layer comprises a conductive metallic film. 57.The method of claim 56, wherein said conductive metallic film has athickness of less than or equal to 1 mil.
 58. The method of claim 56,wherein said conductive metallic film has a resistivity less than 1×10⁻⁵Ohm-meter.
 59. The method of claim 56, wherein said conductive metallicfilm comprises conductive particles selected from at least one the groupconsisting of: copper (Cu), silver (Ag), gold (Au), iron (Fe), andnickel (Ni).
 60. The method of claim 56, further comprising applyingsaid conductive metallic film to the backside of a fabricated waferafter said wafer is background and before said wafer is cut intoindividual semiconductor devices.
 61. The method of claim 56, whereinsaid conductive metallic film is deposited by a method selected from thegroup consisting of: electroless plating, electrolytic plating,molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), physical vapordeposition (PVD), chemical vapor deposition (CVD) and metal organicchemical vapor deposition (MOCVD).
 62. The method of claim 31, whereinsaid device is a memory device.
 63. The method of claim 62, wherein saidmemory device is a dynamic random access memory (DRAM) device.
 64. Themethod of claim 31, wherein said device is a logic device.
 65. Themethod of claim 31, wherein said device is a processor device.
 66. Aprocessor system comprising: a processor; a memory device in electricalcommunication with said processor; at least one of said memory deviceand said processor comprising: a semiconductor substrate; at least oneelectrical element fabricated on an upper side of said substrate; aplurality of bias voltage distribution regions fabricated over saidupper side of said substrate for receiving a bias voltage and providingsaid bias voltage to said substrate; and a conductive layer provided ona back side of said substrate.
 67. The system of claim 66, wherein saidelectrical element comprises at least one electrical element selectedfrom the group consisting of: transistors, resistors, capacitors,electrodes, amplifiers, inverters, and gates.
 68. The system of claim66, wherein said conductive layer is electrically coupled to a terminalsupplying said bias voltage.
 69. The system of claim 66, furthercomprising plurality of conductive plugs for respectively coupling saidbias voltage to said distribution regions.
 70. The system of claim 66,wherein said conductive layer comprises a conductive metallic layer. 71.The system of claim 70, wherein said conductive metallic layer has athickness of less than or equal to 10 mil.
 72. The system of claim 70,wherein said conductive metallic layer is secured to the backside ofsaid substrate with a conductive adhesive.
 73. The system of claim 70,wherein said conductive metallic layer is electrically coupled to aterminal for supplying said bias voltage.
 74. The system of claim 70,wherein said conductive metallic layer has a resisitivity less than1×10⁻⁸ Ohm-meter.
 75. The system of claim 70, wherein said conductivemetallic layer comprises at least one material selected from the groupconsisting of: copper (Cu), silver (Ag), alloy 42, gold (Au), iron (Fe),and aluminum (Al).
 76. The system of claim 75, wherein said conductivemetallic layer is formed of at least one material selected from thegroup consisting of: copper (Cu), silver (Ag), alloy 42, gold (Au), iron(Fe), and aluminum (Al).
 77. The system of claim 70, wherein saidconductive metallic layer has a length which exceeds a length of saidsubstrate.
 78. The system of claim 66, wherein said conductive layercomprises a cured conductive paste.
 79. The system of claim 78, whereinsaid conductive paste has a thickness of less than or equal to 1 mil.80. The system of claim 78, wherein said conductive paste has aresistivity less than 1×10⁻⁵ Ohm-meter.
 81. The system of claim 78,wherein said conductive paste comprises a resin with conductiveparticles.
 82. The system of claim 81, wherein said conductive pastecomprises at least one conductive particle selected from the groupconsisting of: copper (Cu), silver (Ag), gold (Au), iron (Fe), andnickel (Ni).
 83. The system of claim 66, wherein said conductive layercomprises an isotropically conductive polymeric film.
 84. The system ofclaim 83, wherein said conductive polymeric film has a thickness greaterthan 1 mil.
 85. The system of claim 83, wherein said conductivepolymeric film has a resistivity less than 1×10⁻⁵ Ohm-meter.
 86. Thesystem of claim 83, wherein said conductive polymeric film comprises atleast one conductive particle selected from the group consisting of:copper (Cu), silver (Ag), gold (Au), iron (Fe), and nickel (Ni).
 87. Thesystem of claim 66, wherein said conductive layer comprises a conductivemetallic film.
 88. The system of claim 87, wherein said conductivemetallic film has a thickness of less than or equal to 1 mil.
 89. Thesystem of claim 87, wherein said conductive metallic film has aresistivity less than 1×10⁻⁵ Ohm-meter.
 90. The system of claim 87,wherein said conductive metallic film comprises at least one materialselected from the group consisting of: copper (Cu), silver (Ag), gold(Au), iron (Fe), and nickel (Ni).
 91. The system of claim 90, whereinsaid conductive metallic film is formed of at least one materialselected from the group consisting of: copper (Cu), silver (Ag), gold(Au), iron (Fe), and nickel (Ni).
 92. The system of claim 66, whereinsaid device is a memory device.
 93. The system of claim 92, wherein saiddevice is a dynamic random access memory (DRAM) device.
 94. The systemof claim 66, wherein said device is a logic device.
 95. The system ofclaim 66, wherein said device is a processor device.
 96. A semiconductordevice comprising: a semiconductor substrate; at least one electricalelement fabricated on said substrate; and a conductive layer provided ona backside of said substrate, said conductive layer forming anelectrical path between said substrate and at least one non-substratearea of said device.
 97. A semiconductor device comprising: asemiconductor substrate; at least one electrical element fabricated onan upper side of said substrate; a plurality of bias voltagedistribution regions fabricated over said upper side of said substratefor receiving a bias voltage and providing said bias voltage to at leastsome portion of said substrate; and a conductive layer provided on abackside of said substrate, said conductive layer forming an electricalpath between said substrate and said bias voltage source.
 98. Asemiconductor device comprising: a semiconductor substrate; at least oneelectrical element fabricated on said substrate; a plurality of biasvoltage distribution regions fabricated over said upper side of saidsubstrate for receiving a bias voltage and providing said bias voltageto at least some portion of said substrate; a conductive metallic layerprovided on a backside of said substrate, said conductive metallic layerwire bonded to a bonding pad of said semiconductor device; and saidbonding pad forming an electrical path between said conductive metalliclayer and at least one other area of said device.
 99. A semiconductordevice comprising: a semiconductor substrate; at least one electricalelement fabricated on said substrate; a plurality of bias voltagedistribution regions fabricated over said upper side of said substratefor receiving a bias voltage and providing said bias voltage to at leastsome portion of said substrate; and a conductive layer provided on abackside of said substrate, said conductive layer in electricalcommunication with a bonding pad of said semiconductor device.